Semiconductor devices are found in many products in the fields of entertainment, communications, networks, computers, and household markets. Semiconductor devices are also found in military, aviation, automotive, industrial controllers, and office equipment. The semiconductor devices perform a variety of electrical functions necessary for each of these applications.
The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each semiconductor die contains hundreds or thousands of transistors and other active and passive devices performing a variety of electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce a package suitable for faster, reliable, smaller, and higher-density integrated circuits (IC) at lower cost. Flip chip packages or wafer level chip scale packages (WLCSP) are ideally suited for ICs demanding high speed, high density, and greater pin count. Flip chip style packaging involves mounting the active side of the die face down toward a chip carrier substrate or printed circuit board (PCB). The electrical and mechanical interconnect between the active devices on the die and conduction tracks on the carrier substrate is achieved through a solder bump structure comprising a large number of conductive solder bumps or balls. The solder bumps are formed by a reflow process applied to solder material deposited on contact pads which are disposed on the semiconductor substrate. The solder bumps are then soldered to the carrier substrate. The flip chip semiconductor package provides a short electrical conduction path from the active devices on the die to the carrier substrate in order to reduce signal propagation distance, lower capacitance, and achieve overall better circuit performance.
During wafer-level manufacturing, the wafer or the components formed over the wafer are easily damaged. For example, if the wafer is too thin, wafer breakage or wafer slip may occur during wafer handling resulting in significant yield loss and fabrication downtime. In an effort to increase the strength and durability of the wafer, a temporary wafer carrier is often bonded to the wafer to provide additional physical support. Although the temporary wafer carrier minimizes the likelihood of wafer damage, bonding and then de-bonding the carrier during wafer-level processing takes time and increases the duration and cost of manufacture. Furthermore, the bonding material used to attach the temporary wafer carrier limits the maximum temperature that can be used during wafer-level fabrication. Contemporary temporary bonding materials require the fabrication process to take place below 200° C., for example.